In the manufacturing of various types of integrated circuits (ICs), a process referred to as burn-in is employed to reduce failures due to infant mortality. Burn-in accelerates defects by operating the circuitry under extreme operating conditions for a period of time. The time period and conditions (input power cycling, load switching, temperature, etc.) generally vary according to manufacturer and the type of IC.
For very large scale integration (VLSI) designs, operating conditions for burn-in generally include a much higher voltage and temperature than during normal operation for the device. The burn-in test process thus exposes a potential defect in the chip by operating the circuitry under such extreme conditions. For instance, a processor that normally operates at 1.5 V and at a maximum temperature of 110 degrees C., such as when used in a computer, might be burned in at 2.1V and 120 C. These elevated operating conditions accelerate failures due to latent, but not catastrophic manufacturing defects.
In order for burn-in to effectively accelerate the occurrence of these latent defects, however, the device must be operating correctly so that a very high percentage of the circuitry is activated. Accordingly, the burn-in operating conditions maintain substantially all parts of the chip active and then appropriate testcases are run on the chip to verify the functionality under the increased stress operating conditions associated with burn-in. During burn-in, the operating frequency is much slower than during normal operation. Thus, ensuring proper operation of the chip during burn-in can become difficult for certain types of circuitry, and further increases as greater device densities are implemented for ICs.
Domino gates are an example of one type of circuitry that tends to operate deficiently during burn-in conditions. For example, domino gates can fail in the absence of taking explicit steps to protect such circuitry during burn-in. Thus, to help these and other types of circuits operate correctly, supplemental circuitry, such as a keeper circuit, has been developed. A keeper circuits operates to prevent a node or bit from losing its charge, for example, by supplying a voltage at such node. Some types of keeper circuits can impose penalties since large areas may be needed to implement such circuitry, or the operation of the gate can be slowed. Additionally or alternatively, existing keeper circuits may require use of an external signal to implement keeper functions at appropriate times. The extra overhead associated with these and other keeper solutions can further result in decreased performance during normal operation.